The invention relates to a time-discrete signal processor comprising
a signal input for receiving a stream of signal units, PA1 address generating means for, in step with reception of each particular signal unit, generating an associated cycle of microcode addresses MA(i) (i=1, . . . ) for PA1 a microcode store for controlling processing circuitry for processing the signal unit. PA1 base address reproducing means, for in each cycle reproducing a standard sequence of successive base addresses BA(i) (i=1 . . . N), and arranged for feeding the base addresses BA(i) to PA1 microcode selecting means for selecting, in step with each base address and under control of signal data received from the processing circuitry, an associated microcode address MA(i) from a repertory of microcode addresses indicated by the base address BA(i). PA1 index selecting means, for selecting, under control of the signal data, an associated index IA(i), and PA1 index adding means, for adding the base address BA(i) and the selected associated index IA(i), a sum output of the index adding means being arranged for feeding the microcode addresses MA(i)=BA(i)+IA(i) to the microcode store.
Such a time discrete signal processor is known from an article titled "CGE: Automatic Generation of Controllers in the Cathedral II Silicon Compiler" by J. Zegers et at., published in the proceedings of the European Design Automation Conference 1990 (EDAC 90) pages 617-621.
In a time discrete signal processor a stream of discrete signal units is processed. Usually, the signal units are digital, but they may also take other forms, e.g. as analogue charges stored on capacitors, which represent time discrete samples of a signal. Each signal unit is subjected to various processing steps. For example, a typical time discrete signal processing function like filtering requires processing steps like storage of data from the signal units, later retrieval, multiplication with various filter coefficients, and summation of the products.
To execute the processing steps, the processing circuitry comprises a combination of functional units, selected from such components as for example signal busses, arithmetic logic units (ALUs), multipliers, memories, registers, pass gates etcetera.
For many applications, the maximum processing step execution rate of the processor is much greater than the rate at which signal units arrive. This means that it is possible to perform a cycle of many successive processing steps for each arriving signal unit, whereby parts of the processing circuit may be timeshared between different processing steps. In order to perform the required cycle of processing steps a succession of digital control signals needs to be applied to these functional units, for example to open or close pass gates, to program the function of an ALU or to retrieve a specific filter coefficient.
In the known time discrete signal processor, the digital control signals needed at respective instants in the cycle are stored as microcodes in respective addressable locations of a microcode store. By applying the address of a microcode to this store, the microcode is retrieved from it. This microcode is then applied as a control signal to the functional units. Thus, a cycle of addresses, applied to the microcode store, will lead to the execution of a signal processing function under direction of a cycle of control signals.
According to the prior art microcodes which have to be output successively are stored at successive locations. In this case, the cycle of addresses can be generated by means of an incrementing counter. This, however, does not provide for data dependent instruction execution. To accommodate data dependence, the prior an teaches the use of branching. This means that, at least at some branch points in the cycle the next address will not be determined by incrementing, but by branching, i.e by a conditional jump in the microcode address value.
For branching, the known time discrete signal processor contains branch logic for each branch point. This branch logic receives signal data, and from it determines whether a branch is to be executed, and selects the next address. The problem with the branch logic is that it is requires a lot of circuitry, because it must store for all branch points microcode addresses for all branch targets. Because of its complexity the branch logic will moreover tend to be slow.